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Vanguard VME Bus Analyzer, Exerciser and Protocol Checker
Curtiss Wright Controls Defense Solutions’ Vanguard VME Bus Analyzer, a complete solution for VMEbus analysis, detects exercising and protocol errors and supports new VME standards, including 2eSST.
USB, Application Programming Interface, or a PC Ethernet running Windows and BusView graphical user interface controls the bus analyzer. Connecting to Ethernet opens countless opportunities as users can connect to Vanguard analyzers in any area with network connection. Like all Curtiss-Wright Controls’ analyzers, the Vanguard VME may use target system power or power from an external supply. Online help is available.
State Analyzer
With highly advanced (yet simple to use) triggering, filtering and counting capabilities, the Vanguard VME’s State Analyzer captures and displays VMEbus activity in State or Timing modes. Unlike logic analyzers, Curtiss-Wright Controls’ VME Bus Analyzers know the bus protocol and derive the sampling clocks from the bus cycles at the perfect timing, completely tracing all kinds of activity, including arbitration, interrupts, block cycles, RMW cycles, etc.
Exerciser
A powerful Master with a DMA engine, a Slave memory, a System Controller and an Interrupt Generator and Handler is the optional (-VE) Exerciser available for Curtiss-Wright Controls’ Vanguard VME. The flexible and easy-to-use unit allows concurrent operation of all functions. With a flexible script feature, users can make test scripts and automate tasks. Dialogue boxes control the exerciser through the user-interface, automated with the built-in script recording and playback capability with programmable delay and loop functions.
Protocol Checker
Curtiss-Wright Controls’ (formerly VMETRO) Vanguard VME Bus Analyzer’s optional protocol checker (-VP) automatically detects up to 60 VME errors, helping the user discover bus hardware errors without understanding the problem’s nature. The protocol checker can run even while other Vanguard analyzer functions are active. For example, while the protocol checker runs in the background, screening the bus for errors, the state analyzer and the bus utilization statistics can all be active. If the protocol checker is used as the trigger source for the analyzer(s), the state and timing analyzers will give a comprehensive picture of the bus activity around the point when an error was found, allowing the user to identify and correct the problem.
Bus Analyzer, Exerciser & Protocol Checker for VMEbus Features
- Protocol Checker and Exerciser
- Support of VME, VME64, 2eVME and 2eSST
- 2M Sample Trace Buffer at 256 bits
- Networked VME Bus Analyzer (built-in Ethernet port)
- Concurrent and independent operation of all functionsNetworked VME Bus Analyzer (built-in Ethernet port)
| General |
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| VMEbus |
Up to 320 MB/s (2eSST320) |
| Interfaces |
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| USB port |
12 Mb/s |
| Ethernet port |
10/100 Mb/s |
| Power supply requirements |
+5VDC +/-5% from VME connector or from ext. power supply via front panel inlet. |
| Power consumption |
idle: 1.5A (7.5W) VG-VME(-VP) 2.1A (10.5W) VG-VME(-VP)-VE
active: 2.8A (14W) VG-VME(-VP) tbd VG-VME(-VP)-VE |
| Dimensions |
160 x 233.4 mm (6U) |
| Compliant to |
VMEbus Rev. D 1992
ANSI/VITA 1-1994 VME64 Standard
ANSI/VITA 1.1-1997 VME64 Extensions
ANSI/VITA 1.5-2003 2eSST |
| Operating Temperature |
0-50 ºC / 32-248 ºF |
| Measurements |
Temperature: 0-120 °C/ 32-122°F
Voltage: 3.3V, 5V, 12V |
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| Analyzer |
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| Trace Memory |
2M x 256 bits (64 MBytes total) |
| Input channels |
101 bus signals, plus 16 ext. inputs on pin headers. |
| Monitored signals |
A31-01, D31-00, DS1*, DS0*, AS*, LWORD*, DTACK*, BERR*, WRITE*, AM5-0, IRQ7-1*, IACK*, IACKIN*, BBSY*, BR3-0*, BG3-0IN*, BCLR*, RESP*, RETRY*, ACFAIL*, SYSFAIL*, SYSRES*, SYSCLK, XAM7-0, GA4-0, 2eSST_Trf_Rate3-0, SubUnit7-0, 2eSST_Odd. BG3-0IN* also clocked separately, encoded and stored as Bus Level. RMW and Block w/VME64 internally generated. Cross trigger signals from the other functional units are also monitored. |
| Trigger |
8 word recognizers covering all 101 VMEbus signals and 16 Ext. inputs. True Range & NOT operator on Address/Data. Edge Triggering. |
| Range |
8 A64 address ranges, 8 D64 data ranges. Inside/Outside. |
| Sequencer |
16 levels with If, Else, Elsif, Goto, Count, Delay, Trigger, Store, Halt. |
| Trigger position |
0-100%, 1% resolution |
| AS* to Data Counter |
6-bits |
| Cycle Counter |
8-bits |
| Occurrence/delay counters |
3 x 32-bits |
| Trigger Output |
LVTTL level trigger output with programmable polarity, level or pulse. May pulse on each stored sample. Available on pin header in front panel. |
| External Inputs |
8 TTL level inputs on pin header
8 TTL level inputs on front panel |
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| Statistics |
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| Event counters |
8 x 30-bits |
| Real-Time Statistics Counters |
53 x 30-bits counters |
| Time Tag |
Range: 7.5 ns - 1172 min
Resolution: 7.5ns |
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| Exerciser (-VE Option) |
| Master |
Supports normal and block cycles on any BR level, selectable RWD, ROR, ROC or RNE relase options. |
| Slave |
8 MB SDRAM memory, with software controlled base address and window size. |
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| Protocol Checker (-VP Option) |
| VME Violations |
60 Protocol Violations and 3 Protocol Warnings |
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